Micro-scale inductorless maximum power point tracking DC-DC converter

In this study, the authors propose a simple maximum power point tracking (MPPT) DC-DC converter amenable for micro-scale photovoltaic applications. The solution avoids the use of inductors and exploits a charge pump as a voltage boost element. To take into account the temperature dependence of the MPP voltage, a passive temperature compensation circuit is also included. To validate the idea a prototype was realised with commercial off-the-shelf components. A system efficiency better than 83% for output power above 90 mW is obtained. The results show the viability of the proposed approach which could be further improved through a full custom integrated-circuit design

A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

In this paper, a simple while effective methodology to calculate the symbolic transfer function of a multistage amplifier with frequency compensation is proposed. Three general amplifier models are introduced and analyzed, which represent basic topologies found in the literature. For these amplifier models, the symbolic transfer function is derived and specific strategies for the zero and non-dominant pole expressions are presented. The methodology is suited for hand calculations and yields accurate results while offering more intuition into the operation of the widely adopted frequency compensation solutions discussed in the literature. The effectiveness of the proposed approach is validated through various typical cases of study

A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes

Targeting the more recently adopted low-power memories for data-logging operation in IoT nodes, this paper presents a simple reconfigurable dual-branch cross-coupled charge pump (CP) topology in which clock amplitude scaling and modulation of the number of stages are exploited to improve power efficiency and/or change the output voltage without degrading speed performance. The proposed solution allows a reduction of the power conversion losses, maintaining speed, maximum output voltage and silicon area unaltered as compared to the conventional charge pump. Post-layout simulation results confirm the effectiveness of the proposed topology which can be adapted to any other kind of linear charge pump

A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start

In this article, a fully-integrated switched-capacitor DC-DC converter based on a Dickson charge pump able to work with input voltage levels that force the transistors working in subthreshold region is presented. The proposed topology exploits resistors in the charge transfer switch in order to overcome the limits of conventional solutions when working in the subthreshold regime. Post-layout simulations using a 28-nm FD-SOI technology show that the CP can boost an input voltage as low as 50 mV to a maximum output voltage of 270 mV, keeping a settling time about 25X lower than the conventional dual-branch cross-coupled charge pump and a voltage conversion efficiency higher than 76%. The proposed topology is particularly suited for the start-up of power management units supplied by thermoelectric generators

Sub-Femto-Farad Resolution Electronic Interfaces for Integrated Capacitive Sensors: A Review

Capacitance detection is a universal transduction mechanism used in a wide variety of sensors and applications. It requires an electronic front-end converting the capacitance variation into another more convenient physical variable, ultimately determining the performance of the whole sensor. In this paper we present a comprehensive review of the different signal conditioning front-end topologies targeted in particular at sub-femtofarad resolution. Main design equations and analysis of the limits due to noise are reported in order to provide the designer with guidelines for choosing the most suitable topology according to the main design specifications, namely energy consumption, area occupation, measuring time and resolution. A data-driven comparison of the different solutions in literature is also carried out revealing that resolution, measuring time, area occupation and energy/conversion lower than 100 aF, 1 ms 0.1 mm2, and 100 pJ/conv. can be obtained by capacitance to digital topologies, which therefore allow to get the best compromise among all design specifications

Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach

This work proposes a Double Differential (DD) amplifier topology which exploits the advantages of the current-mode approach. DD amplifiers are useful as front-ends in standalone active electrodes for superficial electromyography (sEMG) wearable applications and electroneurography (ENG) measurement devices. Front-ends for these applications need to attain low noise, high common-mode rejection ratio, and high input impedance to measure biopotential signals and can further benefit from low power operation, a small size, and an easily adaptable output. Presently published DD amplifiers are either complex in terms of a high part count, leading to higher power consumption and size, or suffer from limited interference-rejection capabilities and require further analog processing for compatibility with single-ended systems. Therefore, in this work, second-generation current conveyors have been leveraged to obtain a simple topology combining a small active-part count, a high common-mode rejection ratio, and a flexible output stage. The current-mode DD amplifier is presented and analyzed in detail to estimate its parameters and model the effects of nonidealities in the circuit. In order to validate the proposed topology, a discrete-component implementation was realized as a proof-of-concept. The results experimentally demonstrated the properties of the proposed topology and its feasibility for measuring superficial sEMG DD signals.Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señale

A High Efficiency and High Power Density Active AC/DC Converter for Battery-Less US-Powered IMDs in a 28-nm CMOS Technology

In this paper, the design and experimental validation of an active rectifier for ultrasound-based implanted biomedical devices are presented. One of the main contributions is the adoption of an optimized design procedure based on the $g_{m}/I_{D}$ of the transistors. Implemented in a 28-nm CMOS technology and powered by a 0.5-mm thickness and 1-mm2 surface area piezoelectric transducer, the rectifier delivers 1-mW of power to the output load. The adoption of a square wave to drive the transmitting power transducer is experimentally demonstrated to be more power effective. The rectifier exhibits a measured peak power conversion efficiency and a power density equal to 95% and 222mW/ $mm^{2}$ , respectively, revealing itself as the best trade-off between measured power conversion efficiency and power density within the literature of US-powered AC/DC converters

A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices

This paper aims to review the recent architectures of power management units for ultrasound-based energy harvesting, while focusing on battery-less implantable medical devices. In such systems, energy sustainability is based on piezoelectric devices and a power management circuit, which represents a key building block since it maximizes the power extracted from the piezoelectric devices and delivers it to the other building blocks of the implanted device. Since the power budget is strongly constrained by the dimension of the piezoelectric energy harvester, complexity of topologies have been increased bit by bit in order to achieve improved power efficiency also in difficult operative conditions. With this in mind, the introduced work consists of a comprehensive presentation of the main blocks of a generic power management unit for ultrasound-based energy harvesting and its operative principles, a review of the prior art and a comparative study of the performance achieved by the considered solutions. Finally, design guidelines are provided, allowing the designer to choose the best topology according to the given design specifications and technology adopted

A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications

Low-invasive and battery-less implantable medical devices (IMDs) have been increasingly emerging in recent years. The developed solutions in the literature often concentrate on the Bidirectional Data-Link for long-term monitoring devices. Indeed, their ability to collect data and communicate them to the external world, namely Data Up-Link, has revealed a promising solution for bioelectronic medicine. Furthermore, the capacity to control organs such as the brain, nerves, heart-beat and gastrointestinal activities, made up through the manipulation of electrical transducers, could optimise therapeutic protocols and help patients’ pain relief. These kinds of stimulations come from the modulation of a powering signal generated from an externally placed unit coupled to the implanted receivers for power/data exchanging. The established communication is also defined as a Data Down-Link. In this framework, a new solution of the Binary Phase-Shift Keying (BPSK) demodulator is presented in this paper in order to design a robust, low-area, and low-power Down-Link for ultrasound (US)-powered IMDs. The implemented system is fully digital and PLL-free, thus reducing area occupation and making it fully synthesizable. Post-layout simulation results are reported using a 28 nm Bulk CMOS technology provided by TSMC. Using a 2 MHz carrier input signal and an implant depth of 1 cm, the data rate is up to 1.33 Mbit/s with a 50% duty cycle, while the minimum average power consumption is cut-down to 3.3 μW in the typical corner